Updated August 12, 2026 · reviewed against primary sources
Specification
DDR6 specs — what's real so far
There is no ratified DDR6 standard to quote yet. What exists is a published sibling standard (LPDDR6), pre-ratification targets disclosed by JEDEC members, and precedent from how the last two generations landed. This page holds all three apart — every row below says which kind of number you're reading. When JEDEC publishes, the Target rows become Published rows and the date at the top moves.
The numbers
| Spec | Value | Status |
|---|---|---|
| Data rate (initial) | ~8,800 MT/s | Target — industry disclosures |
| Data rate (generation ceiling) | up to ~17,600 MT/s | Target — industry disclosures |
| Bandwidth vs DDR5 | ~2× at maturity | Target, consistent with every prior generation |
| Channel architecture | Finer sub-channel split per module (LPDDR6 uses 24-bit channels as 2×12-bit sub-channels; DDR6 expected to follow the granularity trend) | Published for LPDDR6 · expected for DDR6 |
| Voltage | At or below DDR5's 1.1 V | Expected — efficiency is a stated goal |
| Signaling (NRZ vs PAM) | Not public for the final draft | Unknown |
| Form factor | DIMM continuity expected; CAMM2-class modules are the wildcard | Unknown |
| Ratification | In progress | JEDEC target: 2026 |
How to read pre-ratification numbers
The 8,800–17,600 MT/s range traces to JEDEC-member disclosures made while the spec was being drafted. Those numbers are directionally reliable — members build test silicon against drafts — but launch parts never open at the ceiling. DDR5's spec runs to 8,800 MT/s; it launched at 4,800. Expect the same shape: DDR6 platforms opening near the bottom of the range, with the ceiling arriving over years of platform maturity.
What finer sub-channels actually buy
The clearest architectural signal comes from LPDDR6, which is published: its channel is 24 bits wide, organized as two independent 12-bit sub-channels. Narrower, more numerous channels mean more transactions in flight at once — which is what many-core CPUs and mixed AI workloads starve for. DDR5 already moved this direction (two 32-bit sub-channels per module where DDR4 had one 64-bit channel); the generation trend is unambiguous even where DDR6's exact widths aren't public.